Apparatus and methods for tuning a memory interface

ABSTRACT

The disclosure relates to an integrated circuit including programmable control logic configured to generate at least one data pattern sequence from a number of stored data patterns and using the generated at least one data pattern sequence to at least one of read from and write to at least one memory device. A method includes generating at least one data pattern sequence from a number of stored data patterns and writing and reading the data pattern sequence from and to a memory device.

RELATED CO-PENDING APPLICATION

This application is a continuation of co-pending U.S. patent applicationSer. No. 10/987,499, filed Nov. 12, 2004, entitled “APPARATUS ANDMETHODS FOR TUNING A MEMORY INTERFACE”, having inventors Sagheer Ahmadet al., owned by instant assignee and is incorporated herein byreference.

FIELD OF THE INVENTION

The present disclosure relates to apparatus and methods for tuningmemory interfaces and, more particularly, to a virtual memory client andaccompanying method that tests and tunes performance of a memoryinterface.

BACKGROUND OF THE INVENTION

Memory interfaces that are used to connect a memory device with someother circuit or device, such as an integrated circuit, contain numerousinputs and outputs (such as “pads”, which are the connection points tothe integrated circuit) for data lines used to write and read data to amemory device, as well as clock and strobe signals, and command andaddress data. In particular, a memory interface may be tuned through theuse of adjustable delay lines and by adjusting pad driving strengths tooptimize the performance of the memory interface. This becomesparticularly important when interfacing with memory devices such asdouble data rate (DDR) SDRAMs or other high speed data devices where theaggregation of time and delays degrade the performance of the memoryinterface.

In order to optimize the performance of a memory interface, it is knownto tune or find the optimal values of parameters such as the delay linetiming and pad drive strength in order to optimize the memory interface.The process of tuning the memory interface may be performed manually,but this process is time consuming and requires external equipmentconnected to the memory interface. In order to make tuning less onerous,it is known to employ a built-in self test (BIST or an MCBIST for amemory controller, in particular) on an integrated circuit to test thememory interface without external equipment. Such BISTs, however, aretypically not programmable in a significant manner and are implementedto utilize resources of the chip in which the BIST is located that arenormally used for other functions of the chip. Moreover, known BISTsemploy fixed data patterns to test the memory interface. Accordingly,these BISTs cannot provide deterministic worst case data patterns thatmore likely ensure testing of the memory interface is robust andthorough.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will be more readily understood in view of thefollowing description when accompanied by the below figures and whereinlike reference numerals represent like elements.

FIG. 1 illustrates a system having an integrated circuit employingvirtual memory clients in accordance with the present disclosure.

FIG. 2 illustrates one example of a pre-programmed register utilized inthe circuit of FIG.1.

FIG. 3 illustrates a functional block diagram of one example of avirtual memory client in accordance with the present disclosure.

FIG. 4 is a flow diagram of the operation of one example of a writeengine employed in the virtual memory client illustrated in FIG. 2.

FIG. 5 is a flow diagram of the operation of a read engine used in thevirtual memory client of FIG. 2.

FIG. 6 illustrates a flow diagram of a method for tuning write data andstrobe delays in a memory interface in accordance with an example in thepresent disclosure.

FIG. 7 is a flow diagram of a method for tuning read data/strobe delaysin a memory interface in accordance with and example in the presentdisclosure.

DETAILED DESCRIPTION OF THE PRESENT EMBODIMENTS

The present disclosure relates to memory test logic or programmablevirtual memory client, which is similar to a BIST, but includesprogrammable control logic configured to generate at least one datapattern sequence from a plurality of stored data patterns. Additionally,the virtual memory client includes a virtual memory client control logicconfigured to use the generated at least one data pattern sequence to atleast one of read from and write to at least one memory device.

The disclosed programmable virtual memory client is employable on anintegrated circuit, such as a video graphics processor or other suitableintegrated circuit, for example, and may be configured to automaticallytune delay lines and drive strengths of a memory interface connectingthe integrated circuit to a memory device or for inclusion in the memorydevice or as a separate integrated circuit between another integratedcircuit and memory. The integrated circuit may include one or morevirtual memory clients in accordance with the present disclosure thatinclude programmability allowing efficient generation of deterministicworst case data patterns (or other levels of data patterns) for morerobust testing as well as automatic tuning of the delay line and paddrive strengths in order to account for variables such as the integratedcircuit board variables, the memory device, the ASIC type, and process,voltage and temperature variations.

FIG. 1 illustrates a system 100 including an integrated circuit 102having a memory interface 104 that effects reading and writing of databetween the integrated circuit 102 and a number of memory devices 108,110, 112, and 114. Included in the memory interface 104 are series ofpads (i.e., physical connections to busses 107 between the interface 104and memory devices) 105. The series of pads 105 are configured such thatthe pad strength (the intensity of the signals on the pads) and timedelay may be adjusted or tuned by the memory controller or any othersuitable device, whether in the circuit 102 or external to the circuit102.

The integrated circuit 102 may include a number of memory clients 116,which utilize memory resources of the memory devices. That is, thememory clients 116 read and write data to the memory devices 108, 110,112, 114 via a memory controller 118, a control bus 119, a data bus 121for reading/writing, and the memory interface 104. The integratedcircuit 102 also includes a number of virtual memory clients 120, 122,124, and 126. These virtual memory clients are implemented as hardwareon the integrated circuit 102 and may be substituted for the memoryclients 116 using a multiplexer device (e.g., multiplexers 128, 130,132, and 134) for the purpose of testing and tuning the interface 104switched by an ENABLE signal from the virtual memory clients 120, 122,124, and 126. It is noted, however, that the virtual memory clients maybe implemented in an integrated circuit 102 having no memory clients 116in the circuit 102 or memory clients not yet developed on the chip 102.

Although it is possible to utilize only one programmable virtual memoryclient in order to effect tuning of the memory interface 104, the system100 in FIG. 1 illustrates four virtual memory clients 120, 122, 124, and126. By implementing more than one virtual memory client, the likelihoodis greater that a deterministic worst case data pattern for testing ofthe memory interface will be generated. Each of the programmable virtualmemory clients includes virtual memory control logic 136 that effectsthe functions of the virtual memory client. In addition, each virtualmemory client (120, 122, 124, and 126) contains programmable controllogic and status register 138. In particular, the programmable controllogic and status register 138 is used to program the operation ofvirtual memory client logic 136. In the example of FIG. 1, once avirtual memory client (VMC), such as virtual memory client 120, isprogrammed to run, the VMC 120, in this example, replaces the memoryclient 116 and behaves like a memory read/write client for purposes oftesting and tuning the memory interface 104. In connection with theprogramming of each virtual memory client through the programmablecontrol logic and status register 138, the integrated circuit 102 alsoincludes pre-programmable registers 140 that may be preprogrammed withdata patterns by a user for use in generating data pattern sequencesusable by the virtual memory clients.

In this particular example, the pre-programmable registers 140 mayinclude sixteen 32-bit programmable data registers 202 each containing aparticular pattern of the 32 bits (e.g., DATA PATTERN OH, DATA PATTERNOL, etc.) as illustrated in FIG. 2. Each of the patterns is differentfrom the other patterns stored in the other data registers 202. Althoughsixteen data registers are shown, more or less registers may be used.The use of sixteen data patterns, however, sufficiently ensures thatdata pattern sequences generated by the virtual memory clients will bevaried enough to effectively generate a type of deterministic worst casedata pattern to be sent to the memory interface 104.

FIG. 3 illustrates an example of a functional block diagram offunctional portions within virtual memory client 300. This virtualmemory client 300 shown is exemplary for the virtual memory clients 120,122, 124, and 126 illustrated in FIG. 1. VMC logic 136 includes avirtual memory client control logic 302 used to control operations ofthe virtual memory client 300. Additionally, the virtual memory client300 includes a write engine 304 used to issue memory write requests andsend data pattern sequences to the memory interface 104. A read engine306 is also provided within the VMC logic 136 in order to issue memoryread requests to the memory interface 104 for reading data patternsequences out of the memory devices (e.g., memory device 108). Data readfrom the memory controller 118, which have first been read from thememory devices are fed to the virtual memory client control logic 302.The VMC logic 136 also contains a read/write address generator 308 thatis used to generate addresses for writing to or reading from memorydevices 108 the data pattern sequences during the testing and tuningprocesses. The VMC logic 136 also contains a mismatch informationgenerator 310 used to determine mismatches between data patternsequences written to memory and corresponding data pattern sequencesread from memory.

Within the programmable control logic and status register 138, a datapattern generator 312 is included to receive pattern input data from thedata pattern pre-programmable registers 140 illustrated in FIG. 1. Alsowithin the programmable control logic and status register 138 is aprogrammable control register 314. This control register 314, whichtypically includes two registers, is used to control the data patterngenerator 312 in order to generate programmed data pattern sequences.Each of the control registers within the programmable control register314 has, in this example, an eight data pattern multiplexed selector,which is used to generate two bursts of data for writing data to thememory devices in the case of a write request or for comparing with datasequences read from the memory devices 108 in the case of a request. Inthis example, each burst is 256 bits of data. This number of bits may bemore or less, but the use of more bits ensures the generation of adeterministic worst case data pattern. In particular, by using at leasttwo bursts of data with each burst having 256 bits of a data patternsequence, it is possible to program most known data patterns, from asignal integrity perspective, by repeating bursts of these two datapatterns. According to one implementation, the programmable controlregister 314 generates an odd or first burst that includes four cyclesof 64-bit data. Each of the cycles includes two 32-bit data patternsselected from the pre-programmable registers 140 by the programmablecontrol register 314. Once the selections are communicated by theregister 314 to the data pattern generator 312 as indicated by bus 320,the data pattern generator 312 assembles the cycles into the 256-bitburst and sends the assembled burst to the virtual memory client controllogic 302 as indicated by bus 322 for either writing or comparing.

FIG. 3 also illustrates that the virtual memory client 300 includes astatus register 316, which is used to store mismatch informationgenerated by the mismatch information generator 310 and communicated byconnection 324. In the disclosed example, the status register 316includes 68 bits of readable registers. Specifically, 64 bits ofregister 316 may be used to store the mismatch-data that yielded as aresult of mismatch between the comparison of the received data and theexpected data (which is performed by the read engine 306). Additionally,32 bits of the register 316 may be used to store the 32-bit address ofthe first mismatched address found during a current looping cycle.

Another two bits of the status register 316 may contain priority encodedinformation concerning the result of an ORing operation of each cycle ina burst and for each of the four cycles in the burst. Additionally, onebit of the status register 316 may be used to indicate whether themismatch is associated with the odd or the even burst. Thus, with thesethree bits of information, the exact occurrence of where the mismatch isassociated is stored (i.e., that the mismatch occurs in either the oddor even burst and in which of the four cycles within the odd or evenburst the mismatch has occurred).

Finally, the status register 316 may include a one bit “sticky” registerthat is made “TRUE” in the case of a read mismatch and remains TRUEuntil reset. This one bit of information is polled by the mismatchinformation generator 310, which then issues signal 318 when the bit isTRUE for purposes of signaling a mismatch to a user. As an example, thismismatch signal can be used to cause a signaling light emitting diode,such as diode 142 shown in FIG. 1, to turn on in order to assist a userin tuning the memory interface with a visual indication. Alternatively,the signal 318 could also be used to trigger a continuously recordingexternal signal recording device (e.g., an oscilloscope w/memory) tostop recording, thus capturing what a data signal waveform in theinterface 104 looks like when it fails. Thus, this alternative is anexample where the mismatch is not only communicated by a visualindication to the user, but rather to automated equipment. It this case,the VMC engines can be used as part of a testing apparatus for testingthe memory interface, such as an ATE (automatic test equipment) type ofsystem. This provides a much quicker and more apparent failure signal.One of ordinary skill in the art will appreciate, however, that thesignal 318 may be used to initiate signaling using any suitable deviceto communicate mismatch to a user or suitable testing apparatus.

In order to write and read data pattern sequences to the memory devices,each of the virtual memory client logic 136 include a write engine 304and a read engine 306. FIG. 4 illustrates the operation of the writeengine 304. As shown in FIG. 4, when a write operation is initiated bythe virtual memory client control logic 302, the write engine 304 isinitialized as shown in block 402. The write address is initialized at astarting address to which the virtual memory client will write the datapattern sequences or bursts. After initialization, the write engine 304generates a write tag and accesses the write data pattern sequence asindicated at block 406, where the data pattern generator provides thedata pattern sequence. The write engine 304 next determines whether thenumber of outstanding write acknowledgements (WR-ACKS) is less than apredetermined number N as illustrated in decision block 408. If thereare too many outstanding write acknowledgements, the flow loops back toblock 408 until the number of write acknowledgements has decreased belowthe value N. In the present example, N is equal to 255 based on thewrite buffering capability of the memory controller, but this numbercould be more or less. It is also noted that write engine 304 generatesunique tags for all outstanding write-requests, therefore having biggervalue of N would require more complex logic to generate unique tags.Once the number of outstanding write acknowledgements is less than thepredetermined number N, the write engine 304 sends the write requestover bus 326 to the memory controller 118 as indicated in block 410.

After the write request is sent to the memory controller, the writeengine 304 determines if all write requests, which are based on the userprogrammed control register 314, have been posted to the memorycontroller. If all of the requests have been posted, flow proceeds toblock 414 where the write engine checks to ensure that no outstandingwrite acknowledgements still exist. Once all the write acknowledgementshave been received, the process ends at block 416. It is noted that onceall the writes have been posted, reading is then effected from the sameaddresses to figure out if there is a mismatch (i.e., a failure of thememory interface 104). It is during reading that it is possible todetermine if there is a data mismatch. It is also noted that the writescan be programmed by logic 302 in conjunction with generator 308 tostart from a certain address (START ADDRESS) and end at certain address(END ADDRESS).

Alternatively at decision block 412, if not all the write requests havebeen posted, the flow proceeds to decision block 418 where the writeengine 304 determines whether the current write address is equal to anend address. If not, flow proceeds to block 420 where the writeaddresses incremented by a predetermined programmed value, which isdetermined by the read/write address generator 308. Alternatively,rather than incrementing write addresses, the write address may bedecremented, dependent on the specific write address next programmed bythe read/write address generator 308 and the desired addressingsequence. Flow then proceeds back to block 404 where a new write tag andwrite data pattern based on the next write address is generated. If, atdecision block 418, the write address is equal to the end address,thereby signifying that all of the addresses determined by theread/write address generator 308 have been written to, the next writeaddress is then reset to the starting address, which is the same as theinitialized write address as set previously at block 402. Flow thenproceeds from block 422 back to block 404.

It is noted that the looping sequence of blocks 404, 408, 410, 412, 418,420, and 422 illustrate a looping mechanism of the write engine thatprovides an iterative or recursive functionality whereby the virtualmemory client may continue to write data pattern sequences to thememories for purposes of testing and tuning the memory interface 104. Itis further noted that the addresses determined by the read/write addressgenerator 308 may be all in the same memory device (e.g., memory 108),in two or more different memory devices (e.g., memory 108 and memory110), in the same “channel”, which may contain memory addresses in onememory or multiple memory devices, or in different channels, which mayinclude memory addresses in one or more of the memory devices.

The virtual memory client logic 136 also includes a read engine fortesting data read from the memory devices via the memory interface 104.The process by which the read engine 304 operates is illustrated in FIG.5. As shown in FIG. 5, a flow diagram 500 begins with a start 502 wherea read address is initialized. The flow then proceeds to both blocks 504and 521 in a parallel fashion where processing of two differentoperations is performed simultaneously. In block 504, the read engine306 generates a read tag based on the initial read address. Next, flowproceeds to decision block 506 where the read engine determines whetherany outstanding read requests are greater than a number N. Similar tothe write engine flow in FIG. 4, the read engine 304 checks in block 506to ensure that a predefined number of read requests is not outstandingbefore proceeding. If the number of read requests does not exceed thenumber N flow proceeds to decision block 508. It is noted that thenumber N in the present example of FIG. 5 may be 255 based on the readbuffering capabilities of the memory controller but could also be lesseror greater. It is also noted that read-engine 304 has to generate uniquetags for all outstanding read-requests, therefore having bigger value ofN would require more complex logic to generate unique tags.

At decision block 508, the read engine 306 determines whether a mismatchstop flag has been set by the mismatch information generator 310. Themismatch-stop-flag is initially set as part of generating mismatchinformation as indicated at block 528. If the mismatch stop flag is notset as determined in block 508, flow proceeds to block 510 where theread engine 306 sends a read request 328 to the memory controller 118.Alternatively, if the mismatch stop flag is set, then sending of theread request is skipped and flow proceeds to block 512. At decisionblock 512, the read engine 306 determines whether all read requests havebeen posted. If so, the flow reverts to block 514, which will bediscussed later. In the alternative, flow proceeds to decision block 516where the read engine 306 determines whether the current read address isequal to an end address, which is set by the read/write addressgenerator 308. If not, flow proceeds to block 518 where the read addressis either incremented or decremented, dependent on the selected seriesof read addresses set by the generator 308. Alternatively, if the readengine 306 determines at block 516 that the current read address isequal to the end address, flow proceeds to block 520 where the readaddress is reset to the initial starting address.

As shown in FIG. 5, flow proceeds back to block 504 from either block518 or 520, where a new read tag is generated based on the next readaddress. It is noted that the series of operations in blocks 504, 506,508, 510, 512, 516, 518 and 520 constitute a looping mechanism foriteratively or recursively reading data pattern sequences from thememory devices in order to test and tune the memory interface 104.

Consecutive with this looping mechanism, the read engine 306 alsogenerates expected read addresses and expected data pattern sequencesbased on the expected read addresses as illustrated in block 522 afterdetermining at block 521 whether data has been received from the memorycontroller 104. The data is read from bus 330 into the VMC logic 136 andread engine 306 in logic 136. Additionally as shown at block 521, theread engine 306 continues to poll or wait the memory controller 118 ifno data is read until read data is present on bus 330. The expected readaddresses (RD-ADDRESS), in particular, are generated from returned readtags that have are sent at block 510 in the parallel looping mechanismprocess, discussed previously. The expected data pattern sequences arerequested from and returned by the data pattern generator 312 asindicated at block 524.

The read engine 306 next compares the received read data received atblock 521 with the generated expected data generated at block 522 shownat block 526. If the data are equal or match, flow proceeds to block514. At block 514 the read engine 306 determines whether all of the readrequests are done and whether any outstanding read requests areremaining If read requests are still outstanding, flow proceeds back toblock 521 where additional read data from the memory controllercontinues to be received by the read engine 306. In the alternative, ifthe read requests are finished and no outstanding read requests remain,flow proceeds to block 534 where the read engine waits until otheroperations have finished.

If, at decision block 526, the received data does not match thegenerated expected data, flow proceeds to block 528 where the readengine 306 will trigger the mismatch information generator 310 togenerate mismatch information, which, in turn, updates the statusregister 316. After block 528, flow proceeds to decision block 530 wherethe read engine 306 determines whether a data mismatch and stop isrequested on the mismatch. The reason for this determination is to allowanalysis of the mismatch. If the stop is not requested at block 530,flow proceeds back to block 521 where data continues to be read from thememory controller from bus 330 by the read engine 306 in logic 136.Alternatively, if the stop is requested at block 530, flow proceeds toblock 532 and the read engine 306 directs setting a mismatch stop flag.After the flag is set, flow proceeds to block 534 where the read enginewaits until the affirmative condition of block 514 is met. Once theconditions of 514 and 532 have been met, the read engine process isfinished as indicated by block 536.

Turning back to FIGS. 1 and 3, it is noted that the mismatch informationgenerator 310 in each virtual memory client may issue a mismatch signalto a signaling device such as diode 142, discussed previously. The useof the diode 142 for tuning the memory interface 104 allows a user toadjust different parameters such as the memory clock frequency, voltagelevels, ambient temperature or internal parameters while the virtualmemory clients are working in one or both of the read and write loopingmechanisms, discussed above in connection with FIGS. 4 and 5. If morethan one virtual memory client is being used, the mismatch signals fromtwo or more of the virtual memory clients may be ORed together, asindicated by OR gate 144 in FIG. 1 and sent to a pad 146 that drives thesignaling device, such as the light emitting diode 142. It can be usedto trigger a continuously recording external signal recording device(oscilloscope w/memory) to stop recording, thus capturing what thesignal waveform looks like when it fails.

Each of the virtual memory clients may also include automated tuning ofthe delay lines and pad drive strengths with programming within virtualmemory client control logic 302. For this purpose, FIG. 3 illustratesthat the virtual memory control logic 302 issues controlled programminginformation to the memory interface via bus 332 that directs the memorycontroller 118 to change parameters of the memory interface 104. Thecontrol logic 302 may tune the write and read delays of the particularpads in the series of pads 105 in the memory interface 104 as well asthe strength values. The tuning process is iterative and repeats untilthe memory interface 104 is tuned such that no mismatch is registeredwithin the virtual memory client.

FIG. 6 illustrates an exemplary process by which the virtual memoryclient logic 302 tunes the write data and accompanying strobe delays. Inthe present example, this tuning is performed prior to tuning the readdata and strobe delays, but it is noted that one of ordinary skill inthe art may contemplate tuning only the write data and accompanyingstrobe delays or the read and accompanying strobe delays, or tune theread data and strobe delays prior to the write data and strobe delays.

As shown in FIG. 6, a flow diagram 600 begins at block 602. At block604, the clock of the memory interface is set to a desired target clockrate. Next, at block 606, the control logic 302 directs the memorycontroller 118 to synchronize (i.e., reset) the memory devices. Thelogic 302 then directs the memory controller 118 to cycle throughvarious write data and strobe delay settings and also write out thegenerated pattern sequences from write engine 304 to different memorypositions or locations as indicated at block 608. The control logic 302then directs the memory controller 118 to set the memory interface clockto a clock rate lower than the target clock rate. The reason forreducing the clock rate ensures that data to be read will be accurateand without errors.

In block 612, the memories are once again reset as shown in block 612,and “safe” values (i.e., values where the likelihood of mismatches isgreatly reduced) are set for the read data and strobe delays asindicated at block 614. The data pattern sequences are then read backfrom the memories via the interface 104 to the virtual memory controllogic 302 via the read engine 306 as indicated at block 618. These datapattern sequences are the sequences written out previously at block 608.The control logic 302 then determines a composite information based onany mismatched information that is determined by the read engine 306 inconjunction with the mismatch information generator 310. This compositeinformation is then used by the logic 302 to communicate an optimalsetting for each byte in each channel for the write strobe and datadelays as indicated in block 620. The memory controller 118 thenprograms the individual write strobe and data delays received from thecontrol logic 302 within the memory interface 104 as indicated in block622. Once the write strobe and data delays in the memory interface areset, the write tuning procedure ends as indicated at block 624.

FIG. 7 illustrates an exemplary procedure performed by the control logic302 to tune the read data and strobe delays within the memory interface104. As shown in the flow diagram 700, the procedure is initialized atblock 702. After initialization, the control logic 302 directs thememory controller 118 via bus 332 to set the memory interface clock to atarget clock rate as indicated in block 704. The control logic 302 thendirects the memory controller 118 to reset the memory devices at block706. After the memories are reset, the write engine 304 writes out a setof data pattern sequences to the memory or memories via bus 326 as shownin block 708. The memory controller 118, based on control signals fromthe control logic 302, then cycles through various read data and strobedelays as shown in block 710. Additionally, as the memory controllerscycling through the various read data and strobe delays, the read engine306 reads back the data pattern sequences written out to the memories inblock 708. Moreover at block 710, the read engine 306 via the mismatchinformation generator 310 records data match and mismatch information.

From the recorded match and mismatch information, the control logic 302then processes this information in order to determine optimal settingsfor the read strobe and data delay lines as indicated at block 712. Thecontrol logic 302 then directs the memory controller 118 to program theread strobe and data delay lines via bus 332 to the optimal valuedetermined in block 712. Once the read data and strobe delays are set,the procedure ends at block 716.

It is also noted that after setting the write and read data and strobedelays using the procedures of FIGS. 6 and 7, for example, the virtualmemory client control logic 302 may then signal the memory controller118 to set the final clock rate, which will preferably be close to orequal to the target clock rate.

Although the presently disclosed system employing programmable virtualmemory clients is described in the context of tuning a memory interface,such as memory interface 104, one of ordinary skill in the art willappreciate that the pre-programmable virtual memory clients may also beused to test the memory devices (108, 110, 112 and 114, for example)themselves. In such case, a user would define start and end addresseswithin the read/write address generator 308 to utilize all availablememory space in a particular channel. Each of the virtual memory clientswould then target only a respective signal channel and all four of thevirtual memory clients could then be run to cover all four channels.

It is also noted that one of ordinary skill in the art may contemplateprogramming the virtual memory client to generate even more variationsin the data pattern sequences. For example, the first virtual memoryclient 120 would write into a row of addresses in a memory 108, thesecond virtual memory client 122 into the next row of addresses of thememory 108, the third virtual memory client writing into a next row ofaddresses, and so on.

The above detailed description of the examples described therein hasbeen presented for the purposes of illustration and description only andnot by limitation. It is therefore contemplated that the presentapplication cover any and all modifications, variations or equivalentthe fall within the spirit and scope of the basic underlying principlesdisclosed above and the appended claims.

1. An integrated circuit comprising: programmable logic configured togenerate one or more bursts to access a memory device; generatecontrolled programming information to change parameters of a memoryinterface responsive to mismatch information; issuing the controlledprogramming information to the memory interface; based on the controlledprogramming information, automatically tuning the memory interface byautomatically adjusting a delay of at least one physical connection ofthe memory interface by automatically updating a signal strength levelof the at least one physical connection wherein the automatically tuningcycles through a plurality of write and/or read data and strobe delaysettings until no data mismatches are determined.
 2. The integratedcircuit as defined in claim 1, further comprising: a pre-programmabledata register configured to receive programming of the plurality ofstored data patterns.
 3. The integrated circuit as defined in claim 1,wherein the programmable logic further includes a programmable addressgenerator configured to generate at least one of a read and writeaddress to the at least one memory device.
 4. The integrated circuit asdefined in claim 1, wherein the logic is further configured to execute alooping routine where the programmable logic continuously reads datapatterns between predefined starting and ending memory addresses.
 5. Theintegrated circuit as defined in claim 4, wherein the logic is furtherconfigured to determine an expected read data pattern sequence andcompares the read data pattern sequence with the expected read datapattern sequence and determines whether a data mismatch has occurredbased on the comparison.
 6. The integrated circuit as defined in claim3, wherein the programmable logic further includes a mismatchinformation generator configured to determine mismatches between datawritten to the at least one memory and data received from the at leastone memory during the looping routine and issue a signal indicatingfailure of the memory interface when a mismatch is determined.
 7. Theintegrated circuit as defined in claim 6, further comprising a signalingdevice responsive to the signal indicating failure of the memoryinterface.
 8. A method for testing a memory comprising: generating oneor more bursts to access a memory device; generating controlledprogramming information to change parameters of a memory interfaceresponsive to mismatch information; issuing the controlled programminginformation to the memory interface; based on the controlled programminginformation, automatically tuning the memory interface by automaticallyadjusting a delay of at least one physical connection of the memoryinterface by automatically updating a signal strength level of the atleast one physical connection wherein the automatically tuning cyclesthrough a plurality of write and/or read data and strobe delay settingsuntil no data mismatches are determined.
 9. The method of claim 8,further comprising: programming the plurality of stored data patterns.10. The method of claim 8, comprising executing a looping routine tocontinuously read data patterns between predefined starting and endingmemory addresses.
 11. The method of claim 10, comprising determining anexpected read data pattern sequence and comparing the read data patternsequence with the expected read data pattern sequence and determiningwhether a data mismatch has occurred based on the comparison.
 12. Themethod of claim 8, comprising determining mismatches between datawritten to the at least one memory and data received from the at leastone memory during the looping routine and issuing a signal indicatingfailure of the memory interface when a mismatch is determined.